A. Field of the Invention
The present invention relates to semiconductor devices and the method of manufacturing the semiconductor devices.
B. Description of the Related Art
As one of the insulated-gate semiconductor devices, an insulated-gate bipolar transistor (hereinafter referred to as an “IGBT”) that employs a trench-gate structure for the front surface device structure is well known to the persons skilled in the art. Now the manufacturing method for manufacturing an IGBT having a conventional trench-gate structure (hereinafter referred to as a “trench IGBT”) will be described below exemplary in connection with a trench IGBT including metal electrodes on both semiconductor substrate surfaces.
FIGS. 11 and 12 are the cross sectional views of a conventional semiconductor device on the way of manufacture thereof. In FIGS. 11 and 12, the active region of the trench-gate IGBT is shown, but the breakdown-withstanding structure surrounding the active region is not. (In FIG. 1, FIGS. 4 through 9, and FIGS. 13 through 15, only the active region is shown similarly). The active region is a region through which a current flows in the ON-state of the semiconductor device. The breakdown-withstanding structure is a structure that relaxes the electric field strength in the pn-junction plane and realizes a desired breakdown voltage.
As shown in FIG. 11, the front surface device structure, including gate electrode 2, gate insulator film 3, channel region 4, and source region 5, is formed through the general manufacturing process in the front surface of the active region in the semiconductor substrate that works as drift region 1. Simultaneously with forming the front surface device structure of the trench IGBT in the active region, the front surface device structure (not shown) of the breakdown-withstanding structure is formed such that the breakdown-withstanding structure surrounds the active region. Interlayer insulator film 107 is formed on the front surface of the semiconductor substrate by the chemical vapor deposition method (hereinafter referred to as the “CVD” method).
Contact hole 111 is formed through interlayer insulator film 107 by photolithography. Channel region 4, in which source region 5 is formed, and a part of source region 5 formed in channel region 4 are exposed to contact hole 111. Contact hole 111 is an opening, through which the metal electrode layer formed on the front surface of the semiconductor substrate is connected to channel region 4 and source region 5 in the late step.
Then, metal electrode layer 108 made of aluminum (Al) and such a metal is deposited on interlayer insulator film 107 by sputtering as shown in FIG. 12. By the deposition, metal electrode layer 108 is buried in contact hole 111 and connected to channel region 4 and source region 5 through contact hole 111. Metal electrode layer 108 is patterned by photolithography and annealed thermally to provide metal electrode layer 108 with stable adhesiveness and excellent electrical performances.
A passivation film (not shown) is formed on the front surface of the semiconductor substrate. The passivation film is patterned by photolithography to expose metal electrode layer 108. A pretreatment and a zincate treatment are conducted to form a metal plating layer on metal electrode layer 108. After the treatments, a metal plating layer (not shown) is formed on metal electrode layer 108 by electroless plating. A not-shown collector region and a not-shown back surface electrode are formed on the back surface of the semiconductor substrate. Thus, a vertical trench IGBT is completed.
In the proposed method for manufacturing a semiconductor device including a metal electrode layer on the front surface of a semiconductor substrate, a pattern is formed through a resist in the oxide film deposited on the semiconductor substrate. Then, the oxide film is etched by isotropic dry etching for half the thickness thereof. Further, a contact hole is formed by anisotropic dry etching such that the contact hole reaches semiconductor substrate. Aluminum is deposited on the contact hole to form an aluminum electrode. Further, an overcoat film is formed on the aluminum electrode (cf. Japanese Unexamined Patent Application publication No. 2003-152075).
The concentrated studies conducted by the present inventor have revealed that problems as described below are caused by the conventional techniques.
FIGS. 13 through 15 are third through fifth cross sectional views of the conventional semiconductor device on the way of manufacture thereof. FIGS. 13 through 15 show the cross sectional structures of the semiconductor device in the manufacturing process subsequent to FIG. 12. According to the conventional method for manufacturing a semiconductor device, a step as high as the interlayer insulator film 107 thickness is caused between interlayer insulator film 107 and the semiconductor substrate exposed to contact hole 111.
When interlayer insulator film 107 is thick, e.g., 0.5 μm or thicker, the step caused between interlayer insulator film 107 and the semiconductor substrate exposed to contact hole 111 is high, impairing the step coverage of interlayer insulator film 107. If the step coverage of interlayer insulator film 107 is impaired, the growth of metal electrode layer 108 by sputtering on the side wall of contact hole 111 will be delayed. Due to the delayed growth, void 112 is caused locally in metal electrode layer 108. Void 112 is a concavity caused in the metal electrode layer 108 surface or a cavity caused in metal electrode layer 108. In FIG. 12, a concavity caused in the surface of metal electrode layer 108 is shown.
When void 112 is caused on metal electrode layer 108, the resist mask used for pattering metal electrode layer 108 gets into void 112. The resist that has gotten into void 112 cannot be removed by an ashing treatment. Therefore, organic residue 113 remains in void 112 as shown in FIG. 13. Residue 113 remaining in void 112 is carbonized by the thermal annealing treatment conducted after forming the pattern of metal electrode layer 108. Carbonized residue 114 sticks to the metal electrode layer 108 surface around void 112 as shown in FIG. 14.
The residue of the passivation film formed on the metal electrode layer 108 surface after forming the pattern of metal electrode layer 108 also remains on the metal electrode layer 108 surface in the same manner as resist residue 114. When residue 114 remains on the metal electrode layer 108 surface as described above, metal plating layer 109 is not formed on the portion of the metal electrode layer 108 surface, to which residue 114 is sticking as shown in FIG. 15. Therefore, in bonding metal plating layer 109 and a wire (not shown) to each other with a solder, the solder extends to the portion of metal electrode layer 108 not covered by metal plating layer 109, and the semiconductor device may break down.
In bonding metal electrode layer 108 and a wire to each other with a solder (although not illustrated) without forming metal plating layer 109, organic residue 114 remaining on the metal electrode layer 108 surface impairs the electric characteristics. For example, organic residue 114 remaining on the metal electrode layer 108 surface lowers the bonding strength between metal electrode layer 108 and the wire. As countermeasures, residue 114 may be prevented from occurring by improving the step coverage of metal electrode layer 108 to prevent void 112 from occurring. In this case however, other problems as described below will be caused.
To improve the step coverage of metal electrode layer 108 enough to prevent void 112 from occurring, metal electrode layer 108 may be deposited on the front surface of the semiconductor substrate by sputtering in a state in which the temperature of the semiconductor substrate is raised. However, when metal electrode layer 108 made of aluminum or a similar metal is formed on the semiconductor substrate surface without interposing any barrier film therebetween, the semiconductor substrate and metal electrode layer 108 will directly contact each other.
If the semiconductor substrate temperature is raised, an alloy spike will be caused in the semiconductor substrate, or silicon will segregate to the boundary between the semiconductor substrate and metal electrode layer 108, increasing the contact resistance. To prevent the increase in contact resistance caused by the alloy spike or the silicon segregation from occurring, it is impossible to raise the semiconductor substrate temperature to 400° C. or higher, because reflow of metal electrode layer 108 can be expected. The problem described above is caused also in the case, in which a void is caused in metal electrode layer 108. The reason for this is as follows. For example, if the surface portion of metal electrode layer 108 is removed by the pretreatment for plating metal plating layer 109 on the metal electrode layer 108 surface, the void inside metal electrode layer 108 will come out to the metal electrode layer 108 surface.
Japanese Unexamined Patent Application publication No. 2003-152075 proposes a method for improving the step coverage of the metal electrode layer. However, this document discloses nothing on the relation between the shape of the contact hole and the interlayer insulator film thickness. Since there is no description of the void caused in the metal electrode layer, the problems described above will be caused if the void occurs in the metal electrode layer.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a semiconductor device, the reliability thereof is high. It would be further desirable to provide a method of manufacturing a semiconductor device, the reliability thereof is high. The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.